1. Field
The present disclosure generally relates to the process of manufacturing a semiconductor chip package. More specifically, the present disclosure relates to an assembly component and a technique for assembling the chip package, which includes a group of chips arranged in a stack, and a ramp component that is at an angle relative to the stack.
2. Related Art
Chip packages that include stacked semiconductor chips or dies can provide significantly higher performance in comparison to conventional individually packaged chips that are connected to a printed circuit board. These chip packages also provide certain advantages, such as the ability: to use different processes on different chips in the stack, to combine higher density logic and memory, and to transfer data using less power. For example, a stack of chips that implements a dynamic random access memory (DRAM) can use a high-metal-layer-count, high-performance logic process in a base chip to implement input/output (I/O) and controller functions, and a set of lower metal-layer-count, DRAM-specialized processed chips can be used for the rest of the stack. In this way the combined set of chips may have better performance and lower cost than: a single chip that includes I/O and controller functions manufactured using the DRAM process; a single chip that includes memory circuits manufactured using a logic process; and/or attempting to use a single process to make both logic and memory physical structures.
However, it can be difficult to assemble chip packages that include stacked semiconductor chips. In particular, existing assembly techniques may be time-consuming and may have low yields (which may increase the cost of the chip package). For example, in many existing assembly techniques the total vertical position error over the stack of semiconductor chips is the sum of the vertical position errors associated with each of the semiconductor chips. As a consequence, the total vertical position error for stacks that include multiple semiconductor chips can become prohibitively large. This may result in tight manufacturing tolerances to reduce the individual vertical position errors (which can increase the cost of the semiconductor dies) and/or may constrain the number of semiconductor chips that can be assembled in a stack (which may limit performance).
Hence, what is needed is a technique for assembling a stack of chips without the problems described above.